PC Engines apu coreboot Open Source Firmware v4.9.0.3

Key changes

Mainline:

  1. Enabled CPU boost feature in runtime configuration. Some platforms seem to have problems with boost thus we decided to make CPU boost runtime configurable.
  2. We have upgraded to coreboot SDK 1.52 in mainline releases.
  3. Configured pull-ups on WLAN_DISABLE# pins on the mPCIe connectors which could cause issues with certain modems (e.g. Quectel EP06) when floating.
  4. Reproducible builds limiation has been eliminated by setting iPXE and Memtest86+ fixed revisions. More details here
  5. Uploaded SHA256 and signatures of all previous firmware releases. SHA256 files and signatures have been uploaded to pcengines.github.io.
  6. Fixed microcode update feature, which broke due to the upstream changes in coreboot. More details here
  7. Added information about ECC memory capability in SMBIOS tables on 4GB platforms. Physical Memory Array structure in dmidecode should report Multi-bit ECC in Error Correction Type field. Note: the ECC is present only on 4GB platforms. Check how to verify
  8. Added interrupt configuration entries for PCIe bridge devices 2.4 and 2.5. The interrupt ocnfiguration for 2 PCIe bridges were not programmed in BIOS. Kernel/OS will not always program it by itself, thus rely on BIOS programmed values in case kernel will not handle that.
  9. Rebased with official coreboot repository commit 7a732b4.

Legacy:

  1. Enabled CPU boost feature in runtime configuration. Some platforms seem to have problems with boost thus we decided to make CPU boost runtime configurable.
  2. Reproducible builds limiation has been eliminated by setting iPXE and Memtest86+ fixed revisions. More details here
  3. Uploaded SHA256 and signatures of all previous firmware releases. SHA256 files and signatures have been uploaded to pcengines.github.io.

Statistics

Files Changed

The chart shows the total files changed from release tag against the rebase point of given release specified in CHANGELOG (CHANGELOG.md and gitlab-ci.yml excluded from statistics). Check the statistics with:

git diff --stat 7a732b4 ':(exclude)gitlab-ci.yml' ':(exclude)CHANGELOG.md'

Addition and Deletion

The chart represents the total line added and deleted on the PC Engines coreboot fork against the rebase point for given release. Check the statistics with:

git diff --stat 7a732b4 ':(exclude)gitlab-ci.yml' ':(exclude)CHANGELOG.md'

Two files have not been included in the diff as mentioned above since they are not a part of coreboot tree.

Testing

Test changes in this release:

  • Added Verify ECC Presence test (1 test-case)
  • Added Install Debian amd64 on SATA storage test (2 test-cases)
  • Fixed ATA kernel boot time measurement automated test regarding missing tools on the booted OS
  • Updated apu5 hardware configuration with Quectel_EP06 LTE module and WLE1216V5-20 WiFi module
  • Verified (manually) OPNsense installation on apu3 platform
  • Verified that USB modem (TL-WN722N) on apu2 USB3.0 port is initialized correctly
  • Verified CPU boost load in terms of hard-locks (38h apu2 stress testing according to blog post method)

Mainline test results

Legacy test results

  • Mainline:
    • PASSED: 318 (+12)
    • FAILED: 14 (-2)
    • PASSED [%]: 95,78% (+0.75%)
  • Legacy:
    • PASSED: 293 (+11)
    • FAILED: 4 (-11)
    • PASSED [%]: 98.65% (+3.7%)

The improvement of the PASSED tests coverage results from adding 3 test-cases and fixing ATA kernel boot time test (resolved #220 issue). The difference in mainline and legacy FAILED tests statistics is caused mainly by XEN tests problems, that are not supported in legacy testing.

Binaries

Mainline

Legacy

See how to verify the signatures on asciinema